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M62463AFP
Dolby Pro Logic Surround Decoder
REJ03F0275-0200 Rev.2.00 Jun 16, 2008
Description
The M62463AFP is a single chip Dolby Pro Logic surround decoder. This LSI has all of required functions for Dolby Pro Logic surround. Note: Dolby and the double-D symbol are trademarks of Dolby laboratories licensing corporation. San Francisco, CA94103-4813, USA. This device available only to licensees of Dolby Lab. Licensing and application information may be obtained from Dolby Lab.
Features
* Includes all functions necessary for Dolby Pro Logic surround Adaptive matrix Input auto-balance Noise sequencer Center mode control ON/OFF, WIDE/NORMAL/PHANTOM Modified Dolby B type noise reduction 4 channel (Lch/Rch/Cch/Sch) / 3 channel (Lch/Rch/Cch) Digital delay Delay time: 15.4 to 51.2 ms * Cch/Sch master volume: 0 to -87 dB / 1 dB step, - * 3-lines MCU control * Space surround such as Disco, Hall and Live * Digital echo for Karaoke function Delay time: 123,184 ms * Current control oscillation circuit for system clock
System Configuration
M62463AFP
Lch IN
Input autobalance control S' Noise sequencer L
Lch OUT Rch OUT
Center master volume Surround master volume
Adaptive matrix
R C Center/ operating mode control
Rch IN
Master volume
Lch Rch
L-R L+R 2
7 kHz LPF
Modified S Dolby B-NR
Cch OUT Sch OUT
CENTER
SURROUND
MIC IN
Digital delay
MCU interface
DATA SCK REQ
REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 1 of 16
M62463AFP
BY-PASS
1 2
SW1
Block Diagram
Noise sequencer
SPACE SORROUND
+
PROLOGIC
3 4 1 SPACE SORROUND 3
1
MUTE BY-PASS +/-
4 2
LOUT
L Center mode control
PROLOGIC MUTE
LIN 57 Adaptive matrix R C
WIDE NORMAL PHANTOM OFF
2
ROUT
A/D
LPF
D/A
3
4
LPF
REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 2 of 16
Input balance
Selector
SW2
5
RIN 58 S'
Master volume
4
3
CVOLOUT
L+R 2
L-R
Digital delay SW3 10 Kbit SRAM Modified BNR
1 2
8
SVOLOUT
7 6
SW4 Logic
2
1
Master volume
MICIN SW5
12
F.B.VOL
MCU interface
1
SW6
2
MIC VOL
18
19
20
32
31
33
14
15
16
MICOUT
DATA
SCK
REQ
M62463AFP
Pin Arrangement
BNR IN
33
DBC3
DBC2
35
48
47
46
45
44
43
42
41
40
39
38
37
36
34
RLC8 RLC6 LBPF2 LBPF1 RBPF2 RBPF1 LT RT LIN RIN AVcc VREF IREF NGC3 NGC2 NGC1
49 50 51
Full wave rectifier
Log difference amplifiers
Dual-time constant and threshold switches
Modified B-type NR decoder
DBC1
PSC4
PSC1
PSC5
PSC2
PSC6
PSC3
RLC3
RLC7
RLC4
RLC1
RLC2
RLC5
32 31
FBIN LPF2 OUT LPF2 IN2 LPF2 IN1 DAINT OUT DAINT IN DACONT ADCONT ADINT OUT ADINT IN LPF1 OUT LPF1 IN2 LPF1 IN1 DSEL OUT MICOUT DVss
LPF
30 29 28
L+R L-R
F.B. VOL
52 53
BPF
L
C
R
10 Kbit SRAM
VCA
Combining S' networks
BPF
54 Selector 55
Auto balance
D/A
27 26
Center mode control
LRC
L-R
Logic
VCA
56 SERVO 57
22 k
SW4
2 1
SW5
25
A/D
L+R 2
3
4
24 23
58
22 k
59
VREF
AVcc
1
2
SW3
LPF SW6 CLK
22 21 20
1
23 1 4
2 1
3 4
61 62
IREF
SW2
Noise sequencer
MIC VOL
SW1
2
60
+
+/-
19 18
DVss
63 64
VOL
VOL
AGND DVdd
MCU interface
DATA SCK REQ
17
L
R
C
S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ROUT
CVOLOUT
CVOLIN
COUT
SOUT
LOUT
SVOLIN
SVOLOUT
AGND
DATA
CMC
SCK
VREFD
REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 3 of 16
MICIN
DVdd
REQ
M62463AFP
Functional Description
Function 1 Fundamental function for Dolby Pro Logic surround decoder Description Adaptive matrix Input auto-balance Noise sequencer Center mode control ON/OFF WIDE/NORMAL/PHANTOM Modified Dolby B type noise reduction 4 ch (L, R, C, S), 3 ch (L, R, C) mode switch 10-Kbit RAM 15.4, 20.5, 25.6, 29.2 ms (for Dolby Pro Logic surround) 51.2 ms (for space surround) Digital delay circuit can be used for space surround such as a Disco, Hall or Live, and Karaoke echo 123,184 ms Delay signal feedback volume -3 to -21 dB / 3 dB step, and - Internal microphone volume 0 to -18 dB / 3 dB step, and - 0 to -87 dB / 1 dB step, and - Bypass the decode circuit Mute the Lch and Rch output Controlled by 3-lines serial data from MCU Including the chip address (2-bit) Including the oscillation circuit without external parts
2 3
RAM for digital delay Surround delay time
4 5 6 7 8 9 10 11 12
Circuit for space surround Echo delay time Feedback volume Microphone volume Cch/Sch master volume Bypass switch Output mute MCU interface Current control oscillation circuit
REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 4 of 16
M62463AFP
Absolute Maximum Ratings
(Ta = 25C, unless otherwise noted)
Item Supply voltage Power dissipation Operating temperature Storage temperature Vcc Vdd Pd Topr Tstg Symbol Ratings 10.5 6.5 1 -20 to +75 -40 to +125 Unit V V W C C
Recommended Operating Condition
Item Supply voltage Input voltage (L) Input voltage (H) Symbol Vcc Vdd VIL VIH Min 8 4.5 0 Vdd - 1 Typ 9 5 -- -- Max 10 5.5 0.8 Vdd Unit V V V V Condition
14, 15, 16 pin 14, 15, 16 pin
REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 5 of 16
M62463AFP
Electrical Characteristics
(Ta = 25C, Vcc = 9 V, Vdd = 5 V, Cch volume = 0 dB, at C-OUT 0 dBd = 300 mVrms, f = 1 kHz, unless otherwise noted)
Item Total Circuit current Circuit current Auto-Balance Capture range Error correction Adaptive Matrix Output level accuracy relative to Cch Matrix rejection Head room Total harmonic distortion S/N ratio Noise Sequencer Output noise level Symbol ICC IDD CPR CER VoL MR HRAM THDAM SNAM Min -- -- -- -- -0.5 25 15 -- 70 Typ 25 13 5 4 0 40 17 0.05 80 Max 40 25 -- -- 0.5 -- -- 0.2 -- Unit mA mA dB dB dB dB dB % dB L, R, Sch output L, R, C, Sch output L, R, C, Sch output L, R, Cch output, 30 kHzLPF Rg = 0 , weighted CCIR/ARM, 4 ch mode L, R, C, Sch output Test Conditions No signal No signal
Vno
-15
-12.5
-10
dB
-0.5 0 0.5 dB L, R, Sch output Noise level accuracy relative Vno to Cch Modified B Noise Reduction (Sch volume = 0 dB, 0 dB reference is 300 mVrms/100 Hz at S-Out) Gain between input and output Decode character 1 Decode character 2 Decode character 3 Decode character 4 Total harmonic distortion Head room S/N ratio Cch/Sch Master Volume Maximum attenuator Minimum attenuator Volume step Volume cross-talk Output noise voltage Line (Bypass mode) Total harmonic distortion S/N ratio Line cross-talk Input impedance VGNR DEC1 DEC2 DEC3 DEC4 THDNR HRNR SNNR -- -1.6 -3.0 -4.9 -6.8 -- 15 68 5.1 -0.1 -1.5 -3.4 -5.3 0.07 17 78 -- 1.4 0 -1.9 -3.8 0.3 -- -- dB dB Vin = 0 dBd, f = 100 Hz Vin = 0 dBd, f = 1.0 kHz Vin = -15 dBd, f = 1.4 kHz Vin = -20 dBd, f = 1.4 kHz Vin = -40 dBd, f = 5.0 kHz Vin = 0 dBd, f = 1 kHz, 30 kHzLPF THD = 1% Rg = 0 , weighted CCIR/ARM ATT = -, Vi = 2 Vrms ATT = 0 dB ATT = 0 to -40 dB ATT = -40 to -87 dB R input/CVOL, SVOL output ATT = - L, Rch output, 30 kHzLPF L, Rch output L input/R output, R input/L output
% dB dB
ATTmax ATTmin VOLS1 VOLS2 CTVOL VnoVOL THDLN SNLN CTLN Zi
-- -3.0 0.5 0.2 68 -- -- 95 70 11
-95 0 1.0 1.0 83 2.6 0.002 100 80 22
-87 3.0 1.5 1.8 -- 5.2 0.05 -- -- 44
dB dB dB dB dB Vrms % dB dB k
REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 6 of 16
M62463AFP (Ta = 25C, Vcc = 9 V, Vdd = 5 V, Vin = 200 mVrms, f = 1 kHz, unless otherwise noted)
Item Digital Delay Input/output voltage gain Delay time Total harmonic distortion Symbol GvD Td THDD Min -8.1 17.4 -- -- -- -- -- -- 0.7 6.0 Typ -5.1 20.5 0.5 1.2 3.0 -92 -84 -80 1.0 7.0 Max -2.1 23.6 0.9 2.2 5.6 -80 -70 -65 -- 8.0 Unit dB ms % Test Conditions LIN-LPF2OUT, surround L - R Td = 20.5 ms 30 kHz LPF Td = 20.5 ms Td = 51.2 ms Td = 184 ms Vin = 0 Vrms Td = 20.5 ms JIS-A Td = 51.2 ms Td = 184 ms THD = 10% Td = 15.4 to 51.2 ms Gv = -3 dB (Dolby Pro Logic mode) Td = 123,184 ms (Echo mode) Gv = -3 dB ATT = - ATT = -3 dB
Output noise voltage
NoD
dBV
Maximum output voltage LPF cut-off frequency
Vomax LPFfc
Vrms kHz
-- Feedback Volume Maximum attenuation Minimum attenuation Volume step Microphone Volume Maximum attenuation Minimum attenuation Volume step Output noise voltage FBATTmax FBATTmin FBVOLS MICATTmax MICATTmin MICVOLS VnoMIC -- -6.0 -- -- -3.0 -- --
3.0
--
kHz
-70 -3.0 3.0 -70 0 3.0 2.0
-60 0 -- -60 3.0 -- 4.0
dB dB dB dB dB dB Vrms
ATT = - ATT = 0 dB ATT = -
REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 7 of 16
M62463AFP
Serial Data Control Format
(1) Data input format DATA is read at the rising edge of SCK, and loaded last 16 bits at the rising edge of REQ.
DATA SCK REQ
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 "H"
D0 L
D1 L
D2
D3
D4
Pro Logic mode
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14 L
D15 H
Mode set
Center mode
Autobalance set to "L"
Sch volume
H H L H
Delay time Noise sequencer
Cch volume
Chip address
Surround/echo mode Test mode (user inhibit)
(2) Control condition
No. 1 2 3 4 5 6 7 8 9 Control Mode Mode set Pro Logic mode Center mode Delay time Auto-balance Noise sequencer Surround/echo mode Cch/Sch volume Chip address Contents Normal stereo/Dolby Pro Logic/space surround or echo/mute 4 ch Pro Logic/3 ch stereo Wide/Normal/Phantom/OFF 15.4, 20.5, 25.6, 29.2, 51.2 ms (for surround) 123,184 ms (for echo) Input auto-balance ON/OFF ON/OFF Lch/Rch/Cch/Sch Delay input L - R/(L + R) / 2 /MICin Feedback volume, microphone volume, delay output mixing 0 to -87 dB / 1 dB step, and - Input data effect or not
(3) Set conditions Mode Setting (D0 = "L", D1 = "L")
D2 L L H H D3 L H L H Condition Normal stereo (bypass) Dolby Pro Logic surround Space surround/echo Output mute
Pro Logic Mode Setting (D0 = "L", D1 = "L")
D4 L H Condition 4 ch Pro Logic 3 ch stereo
Center Mode Setting (D0 = "L", D1 = "L")
D5 L L H H D6 L H L H Condition Wide Normal Phantom OFF
REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 8 of 16
M62463AFP Delay Time Setting (D0 = "L", D1 = "H")
D2 L L L L H H H D3 L L H H L L H D4 L H L H L H L Delay Time 15.4 ms 20.5 ms 25.6 ms 29.2 ms 51.2 ms 123 ms 184 ms Sampling Frequency 500 kHz 500 kHz 400 kHz 333 kHz 200 kHz 83.3 kHz 55.6 kHz LPF Cutoff Frequency 7 kHz
3 kHz
Auto-Balance Setting (D0 = "L", D1 = "H")
D5 L H Condition Auto-balance OFF Auto-balance ON
Noise Sequencer (D0 = "H", D1 = "L")
D2 L H D3 -- L L H H D4 -- L H L H Noise sequencer OFF Noise sequencer ON Condition Lch Rch Cch Sch
Surround/Echo Mode (D0 = "H", D1 = "L") Surround/Echo Mode Switch
D5 L H Condition Surround Echo
Delay Input
D6 L H Delay Input L-R (L + R) / 2
Delay Mixing Polarity
D7 L H Mixing Polarity L+ delay signal/R+ delay signal L+ delay signal/R- delay signal
Feedback Volume
D8 L L L L H H H H D9 L L H H L L H H D10 L H L H L H L H Volume -3 dB -6 dB -9 dB -12 dB -15 dB -18 dB -21 dB -
Microphone Volume
D11 L L L L H H H H D12 L L H H L L H H D13 L H L H L H L H Volume 0 dB -3 dB -6 dB -9 dB -12 dB -15 dB -18 dB -
REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 9 of 16
M62463AFP Relation Between Mode Setting and Switch Condition
Pro Logic Mode (D0 = L, D1 = L) D4 X L H X X Mute Note: X: L or H X Surround/Echo Mode (D0 = H, D1 = L) D5 X X L (Surround) H (Echo) X D6 X X L H X X SW1 1 3 SW2 1 3 Switch Condition SW3 SW4 2 1 2 1 2 2 4 1 2 3 4 4
Mode Setting Normal stereo (bypass) Dolby Pro Logic surround Space surround/echo
SW5 OFF OFF ON OFF OFF
SW6 2 2 2 1 2
2 2 Delay mixing ON 1 1 Delay mixing OFF 4 4
Sch Volume Setting (D0 = "L", D1 = "L"), Cch Volume Setting (D0 = "L", D1 = "H")
Volume Level 0 dB -2 dB -4 dB -6 dB -8 dB -10 dB -12 dB -14 dB -16 dB -18 dB -20 dB -22 dB -24 dB -26 dB -28 dB -30 dB -32 dB -34 dB -36 dB -40 dB -44 dB -48 dB -52 dB -56 dB -60 dB -64 dB -68 dB -72 dB -76 dB -80 dB -84 dB - D7 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H D8 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H D9 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H D10 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H D11 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H Volume Level 0 dB -1 dB -2 dB -3 dB D12 L L H H D13 L H L H
Chip Address
D14 L Others D15 H Data Read Enable Unable
REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 10 of 16
M62463AFP (4) Data timing
t1, t2
90%
DATA
10%
t6 t1 t4
t7 t2
90%
SCK
10%
t5 t3 t9 t8
t10
90%
REQ
10%
t1
t2
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
Name Signal rise time Signal fall time SCK clock width SCK "H" pulse width SCK "L" pulse width DATA setup time DATA hold time REQ rise hold time REQ "H" pulse width SCK setup time
Min -- -- 2 0.8 0.8 0.8 0.8 1.6 0.8 1.6
Typ -- -- -- -- -- -- -- -- -- --
Max 0.5 0.5 -- -- -- -- -- -- -- --
Unit s s s s s s s s s s
REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 11 of 16
M62463AFP
Level Diagram
(1) Dolby Pro Logic surround mode
Cch LIN
Input balance Adaptive matrix Center mode control Volume (ATT = 0 dB) Ladder Buffer
CVOLOUT
RIN
Signal level
-3 dB
0 dB
-2.5 dB
0 dB
Vref = 4.5 V
Vref = 2.5 V
Sch
S'
LIN
Input balance Adaptive matrix
1
SW4 Digital delay Modified BNR
1
SW3
Volume (ATT = 0 dB) Ladder Buffer
SVOLOUT
RIN
Signal level
-3 dB
0 dB
-5.1 dB
-5.1 dB
0 dB
-2.5 dB
0 dB
Vref = 4.5 V
Vref = 2.5 V Vref = 2.5 V
Lch, Rch LIN
Input balance Adaptive matrix
RIN
Center mode control
LOUT ROUT
Signal level
0 dB
Vref = 4.5 V Signal level: 0 dB = 300 mVrms (Typ)
REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 12 of 16
M62463AFP (2) Space surround mode
Sch LIN RIN L-R (L + R) / 2 SW4
2 3
Digital delay
Modified BNR
SW3
Volume (ATT = 0 dB) Ladder Buffer
SVOLOUT
Signal level
0 dB
-5.1 dB
-5.1 dB
0 dB
-2.5 dB
0 dB
Vref = 4.5 V
Vref = 2.5 V Vref = 2.5 V
(3) Echo mode
SW4
MICIN
4
Digital delay
0 dB
Signal level
Vref = 2.5 V
MIC volume (ATT = 0 dB) 0 dB
MICOUT
Signal level
Vref = 2.5 V
Signal level: 0 dB = 300 mVrms (Typ)
Notice Relation AVcc and DVdd at power supply Digital Vdd must be supplied less than 0.7 seconds from analog Vcc supply.
AVcc (AVcc DVdd) DVdd Internal reset signal 0.7 s (Min)
Automatic reset cancel
REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 13 of 16
M62463AFP
Application Example
CA18 0.01 R18 4.7 k
MICout
C30 1000 p C32 1
32 31 30
C27 0.1 C29 4700 p
29 28 27
C23 C26 C25 0.1
C21 1000 p C20 4700 p
C18 C19 0.22 1
0.1 0.1
24 23 21 20 19 18 26 25 17
DVss
DATA SCK REQ
LPF
D/A
A/D
LPF
DVdd
R36 330 k
36
CLK
10 Kbit SRAM
35
14
C35 0.047
Modified B-type NR decoder
MCU
34
15
C34 5600 p
MCU interface
33
16
MIC VOL
13
37
SW5
Dual-time constant and threshold switches
1 4 2 L-R 3 L+R 2
SW6
1 2
AGND
12
C37 0.22 C38 0.22
39 38
C12 1
11
+
C36 0.68
10
C39 4.7
40
SW3
1
S
C40 4.7
41
9
VOL
S'
C41 0.22
42
8
2
+
+
Center mode control
RC
C
43
L
Log difference amplifiers
C43 0.1
44
SW2
4
SERVO
Auto balance
VCA
C44 0.047
45
+/-
5
VCA
L
3 2
6
1
+
C45 0.047
46
3 2 1
VOL
4
4
+
47
Full wave rectifier
C47 0.1 C48 0.022
R
2
L+R L-R
Selector
C46 0.1
SW1
C
3
+
AVcc
BPF
53 51 52 49 50
BPF
22 k 22 k
VREF
IREF
L
Noise sequencer
48
+
1
55
57
54
56
58
59
60
61
62
63
C52 0.01
R52 75 k C53 680 p
C54 0.01
C49 0.022
C50 0.1
R61 + 100 k C60 220
C51 680 p
R51 47 k
R54 75 k
R53 47 k
+
64
+
C64 47
RA53 150 k
C55 0.01
C56 0.01
RA51 150 k
C57 10
+
C58 + 10
+
C59
C62 R63 C63 4.7 100 k 6800 p
100
Lin
Rin
AVcc +9 V
Units Resistance: Capacitance: F
REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 14 of 16
+
C42 0.22
Combining networks
R
7
+
C33 1
22
Logic
DVdd +5 V
C13 0.1
F.B. VOL
MICin
SW4
+ +
C10 100
C9 0.1
Sout
C8 10 C6 10
+
C4 10
C3 10 C2 10 C1 10
Cout Rout Lout
M62463AFP
External Parts List
Parts No. C1 C2 C3 C4 C6 C8 C9 C10 C12 C13 C18 CA18 C19 C20 C21 C23 C25 C26 C27 C29 C30 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 Values 10 10 10 10 10 10 0.1 100 10 0.1 0.22 0.01 1.0 4700 1000 0.1 0.1 0.1 0.1 4700 1000 1.0 1.0 5600 0.047 0.68 0.22 0.22 4.7 4.7 0.22 0.22 0.1 0.047 0.047 0.1 Unit F F F F F F F F F F F F F pF pF F F F F F pF F F pF F F pF pF F F F F F F F F Tol. Parts No. C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C62 C63 C64 Values 0.1 0.022 0.022 0.1 680 0.01 680 0.01 0.01 0.01 10 10 100 220 4.7 6800 47 Unit F F F F pF F pF F F F F F F F F pF F Tol. 20% 5% 5% 20% 5% 5% 5% 5% 5% 5%
10%
non-polar 5% 5% 5% 5% 5% 5% 5% 5%
10% 5%
5% 5% 10% 10% 10% 20% 20% 10% 10% 20% 5% 5% 20%
R18 R36 R51 RA51 R52 R53 RA53 R54 R61 R63
4.7 330 47 150 75 47 150 75 100 100
k k k k k k k k k k
10% 10% 5% 5% 5% 5% 5% 5% 1% 5%
REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 15 of 16
M62463AFP
Package Dimensions
JEITA Package Code P-QFP64-14x14-0.80 RENESAS Code PRQP0064GA-A Previous Code 64P6N-A MASS[Typ.] 1.1g
HD *1 D 33
48
49
32
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
*2
HE
E
64 17
Reference Symbol
Dimension in Millimeters
1 ZD
16 Index mark F
c
L Detail F
D E A2 HD HE A A1 bp c e y ZD ZE L
e
y
*3 b p
Min Nom Max 13.8 14.0 14.2 13.8 14.0 14.2 2.8 16.5 16.8 17.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.3 0.35 0.45 0.13 0.15 0.2 0 10 0.65 0.8 0.95 0.10 1.0 1.0 0.4 0.6 0.8
ZE
REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 16 of 16
A1
A
A2
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
(c) 2008. Renesas Technology Corp., All rights reserved. Printed in Japan.
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